A reconfigurable architecture for CNN acceleration using line buffers

Abstract

Computer vision (CV) is experiencing a rapid increase in real-time applications driven by neural network (NN) processing. Convolutional neural networks (CNNs) are the core architecture of advanced CV applications based on artificial intelligence (AI) for autonomous driving, facial recognition, object detection, and information decryption. However, huge computational complexity and continuous memory bandwidth requirements restrict the efficient hardware implementation of CNNs on FPGA platforms. In this paper proposes a reconfigurable systolic CNN architecture using line buffers for enhancing the resource utilization and reducing delay. The proposed architecture dynamically reconfigured to CNN layer requirements, and line buffers improve the data reuse and reduce redundant memory access. In addition, reconfigurable adder and pooling structures are designed to increase the flexibility of accumulation and down sampling operations, supporting various kernel sizes and layers in CNNs. The proposed reconfigurable architecture is hardware-efficient through control signals and adapts to all CNN layers. FPGA implementation of this proposed reconfigurable architecture is performed using LeNet CNN architecture layers. This flexible and low-cost reconfigurable systolic CNN architecture achieves a 15.25% reduction in LUTs utilization, 75% improvement in throughput, and 2.44% reduction in computational delay in LeNet CNN. The implemented LeNet CNN using proposed reconfigurable architecture is suitable for high performance and hardware efficient CNN applications.

The authors' abstract, as published at the source. Scientific Reports, 2026 · DOI ↗