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ACM Transactions on Architecture and Code Optimization· 2026Q2

PPT-GPU 2.0: A Validated, Accurate, and Scalable Modeling of NVIDIA GPUs

Hamdy Abdelkhalik, Atanu Barai, Yehia Arafa, Nandakishore Santhi et al.

Short summary

PPT-GPU 2.0 models NVIDIA GPUs (Volta, Turing, Ampere) with improved accuracy, achieving average errors of 16.4% for active cycles and 5.7% for tensor cores, while simulating 33.51x faster than Accel-Sim.

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Key points

  • PPT-GPU 2.0 models NVIDIA Volta, Turing, and Ampere GPU architectures.
  • Includes detailed modeling of shared memory, tensor cores, and introduces a new 'Balance Model' for occupancy.
  • Achieves average error rates of 16.4% for active cycles, 9.3% for standard pipelines, and 5.7% for tensor cores.
  • Demonstrates a 33.51x speedup in simulation time compared to Accel-Sim.

AI-generated from the title and abstract; the full text is not read.

Abstract

Performance modeling and simulation tools (ModSim) for GPUs continue to be indispensable for performance optimization and a deeper understanding of their complex behaviors and architectures. We detail PPT-GPU 2.0, highlighting significant updates and improvements to PPT-GPU. These include a detailed modeling of the Ampere architecture, including shared memory and tensor cores, while extending coverage across Volta, Turing, and Ampere. Furthermore, we introduce a new GPU occupancy model, “Balance Model”. New performance metrics are also incorporated, including the maximum/minimum number of blocks executed concurrently per streaming Multiprocessor, and the active cycles for each execution pipeline. We evaluate PPT-GPU 2.0 on A100 GPUs, an Ampere architecture. We validate the results using a diverse set of benchmarks compared against real hardware, utilizing NVIDIA Nsight Compute, Accel-Sim (a cycle-accurate simulator), and HyFiSS. PPT-GPU 2.0 demonstrates notable accuracy improvements. For instance, it achieves an average error of 16.4% for active cycles, 9.3% for standard execution pipelines and 5.7% for tensor cores, while maintaining high accuracy for memory hierarchy (8% L1, 21.4% L2 hit rates, and 16.4% for IPC) and execution pipeline modeling. It achieves a 33.51x speedup in simulation time compared with Accel-Sim.

The authors' abstract, as published at the source. ACM Transactions on Architecture and Code Optimization, 2026 · DOI ↗

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Field: Hardware and Architecture

Hardware and ArchitectureComputer Science