IOb-SoC-Linux: An Open-Source, Linux-Capable RISC-V SoC Template for IP Core Development

Abstract

IOb-SoC-Linux is an open-source framework for configuring and generating Linux-capable System-on-Chip (SoC) designs targeting RISC-V processors. Built on the Py2HWSW hardware/software co-design framework, it provides a specialized SoC template that contrasts with bare-metal-focused alternatives, offering a reproducible environment for the design, integration, and testing of Intellectual Property (IP) cores under a full Linux software stack. The primary contribution of IOb-SoC-Linux is an IP Core Linux Driver Development tool that, from a peripheral’s hardware register description, automatically generates a register-access Linux kernel driver, its Device Tree entry, and associated documentation, keeping these software artifacts synchronized with the hardware as it evolves and removing a recurring source of manual, error-prone integration work. The platform supports the open-source VexRiscv and VexiiRiscv RISC-V processors. Beyond the processor subsystem, it integrates the complete infrastructure required for Linux execution: memory management unit, memory controller, peripheral buses, interrupt controllers, timer, UART interface, and configurable IP peripherals. To improve interoperability and reuse, IOb-SoC-Linux adopts the IP-XACT standard (IEEE 1685) alongside the FuseSoC package manager, enabling standardized metadata descriptions and structured package management for hardware IP blocks, with the generated IP-XACT descriptions validated with the open-source Kactus2 IP-XACT tool and imported into Vivado. This allows hardware components to be discovered, configured, and integrated into both the IOb-SoC-Linux environment and the broader open-source hardware ecosystem. The system is designed for portability across multiple FPGA platforms and its generated RTL synthesizes cleanly through an open-source, ASIC-oriented flow to a gate-level netlist, demonstrating its suitability for both FPGA prototyping and ASIC-oriented RTL synthesis.

The authors' abstract, as published at the source. Electronics, 2026 · DOI ↗