Electronics· 2026Q2
Variation-Resilient Low-Cost PUF with Trust-Based Authentication Implemented in 16 nm FinFET for IoT Security
- 0citations
- Q2SCImago
- 2026year
Short summary
A new SRPFD-PUF design using bit self-test (BST) achieves 98.93% reliability under PVT variations and resists machine learning attacks with 47.68–52.46% prediction accuracy, implemented in 16 nm FinFET for low-cost IoT security.
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Key points
- The SRPFD-PUF utilizes bit self-test (BST) for stable CRP selection and response-bit tolerance for improved variation resilience.
- Achieves a minimum simulated logarithmic reliability score of 98.93% under PVT variations (0.675–1.05 V, −40–150 °C).
- Resists machine learning attacks with prediction accuracies ranging from 47.68% to 52.46%.
- Implemented in TSMC 16 nm FinFET, occupying 0.0117 mm² and consuming 0.3089 mW at 100 MHz.
AI-generated from the title and abstract; the full text is not read.
Abstract
Physical Unclonable Functions (PUFs) generate unique chip identifiers from manufacturing variations, but transmissions over public networks can be exploited through eavesdropping. To improve variation resilience, the proposed SRPFD-PUF employs bit self-test (BST) for stable-CRP selection, while response-bit tolerance is considered in an illustrative authentication flow. By minimizing additional circuit overhead, strong baseline PUF metrics are maintained at low hardware cost, supporting integration in Internet of Things (IoT) devices. An illustrative PUF-based authentication flow is presented to demonstrate a potential IoT application; end-to-end protocol implementation and security validation remain outside the scope of this study. The three-condition BST screen yields a minimum simulated logarithmic reliability score of 98.93% under the evaluated PVT conditions within 0.675–1.05 V and −40–150 °C. With the circuit architecture and LFSR configuration disclosed, the evaluated machine-learning attacks yield prediction accuracies of 47.68–52.46%, indicating resistance to the tested modeling methods. The TSMC 16 nm FinFET physical design occupies 0.0117 mm2, while post-layout simulation estimates 0.3089 mW at 100 MHz; no fabricated-silicon measurements are reported.
The authors' abstract, as published at the source. Electronics, 2026 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science