Etkinlik Yoğunluğu Farkındalığı Olan Bölümleme ve Çekirdek Birleştirme Yoluyla GPU Hızlandırmalı Kapı Seviyesi Zaman Bazlı Güç Analizi

Özet (abstract)

Power analysis is crucial in modern chip design flow. Particularly, the time-based power analysis can provide fine-grained power consumption information to facilitate the diagnosis of power issues and guide power optimization accordingly. However, it may take tens of hours to conduct time-based power analysis on modern large-scale circuits, which greatly slows down the power optimization flow. In this paper, we present the first GPU-accelerated gate-level time-based power analysis framework. We propose a novel data structure to enable efficient state-dependent power retrieval. To accommodate the imbalanced event distribution across gates, we propose an event-density-aware partitioning strategy that allocates GPU threads based on gate event density. Finally, we fuse the power computation into a single kernel invocation to reduce redundant work in separate kernels. Experimental results show that our proposed framework achieves high accuracy while delivering up to 37.63 × end-to-end speedup compared to multi-threaded Synopsys PrimeTime PX.

Yazarların özeti; kaynağından alınmıştır. ACM Transactions on Architecture and Code Optimization, 2026 · DOI ↗