ACM SIGARCH Computer Architecture News· 2014
A reconfigurable fabric for accelerating large-scale datacenter services
- 710citations
- 2014year
Short summary
A 6x8 2D torus of Stratix V FPGAs deployed across 1,632 servers boosts Bing search engine ranking throughput by 95% at fixed latency, or reduces tail latency by 29% at equivalent throughput.
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Key points
- Designed and deployed a reconfigurable fabric using a 6x8 2D torus of Stratix V FPGAs across 1,632 servers.
- The fabric connects FPGAs via PCIe and direct 10 Gb SAS cables.
- Accelerated the Bing web search engine's document ranking process.
- Achieved a 95% increase in ranking throughput at fixed latency or a 29% reduction in tail latency at equivalent throughput under high load.
AI-generated from the title and abstract; the full text is not read.
Abstract
Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6x8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server, accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb SAS cables In this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system when ranking candidate documents. Under high load, the largescale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution--- or, while maintaining equivalent throughput, reduces the tail latency by 29%
The authors' abstract, as published at the source. ACM SIGARCH Computer Architecture News, 2014 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science