Science· 2014Q1
A million spiking-neuron integrated circuit with a scalable communication network and interface
- 4,106citations
- Q1SCImago
- 2014year
Short summary
A 5.4-billion-transistor chip integrates 1 million spiking neurons and 256 million synapses, demonstrating a scalable, brain-inspired architecture for real-time neural network applications.
AI-generated from the title and abstract; the full text is not read.
Key points
- Developed a 5.4-billion-transistor chip with 4096 neurosynaptic cores.
- Integrates 1 million programmable spiking neurons and 256 million configurable synapses.
- Features a scalable, tiled architecture with intrachip and interchip communication.
- Achieves 63 milliwatt power consumption for real-time video processing (400x240 @ 30fps).
AI-generated from the title and abstract; the full text is not read.
Abstract
Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.
The authors' abstract, as published at the source. Science, 2014 · DOI ↗
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Field: Electrical and Electronic Engineering
Electrical and Electronic EngineeringEngineering