LSR: Eliminating Loop Control Overhead for Energy-Efficient Processors

Abstract

Loops constitute a small fraction of static code but dominate dynamic execution time and control overhead, posing significant challenges for energy-efficient mobile and embedded processors. This paper introduces Loop Semantic Recognition (LSR) , a microarchitectural technique that dynamically infers loop semantics to eliminate loop control overhead without requiring compiler support or ISA extensions. We further propose three complementary optimizations: Branch Strength Reduction (BSR), Hardware Loop Unrolling (HLU), and Stride Value Prediction (SVP), which progressively remove redundant control instructions, reduce pipeline pressure, and optimize loop execution. Evaluation on TSVC, PolyBench, NPB, and Swan benchmarks demonstrates that LSR and its extensions deliver substantial efficiency and energy benefits. HLU reduces committed instructions by up to 33.23% , while SVP lowers executed instructions by as much as 46.59% . LSR also reduces loop branch mispredictions and consistently decreases dynamic energy consumption, achieving an average processor-wide Energy-Delay Product (EDP) improvement of 8.36% across these four benchmark suites on a 2-wide baseline core. Scaling to a 4-wide core further raises the average EDP reduction to 15.39% . Additionally, LSR maintains consistent effectiveness across compiler optimization levels from -O1 to -O3 , confirming its robustness to code generation strategies. A complementary evaluation of SPEC CPU2017 shows an average EDP reduction of 2.93% , indicating that LSR optimization opportunities also exist in general-purpose workloads. These results are achieved with only 0.45 KB of total storage overhead, confirming LSR as a lightweight and practical solution for improving energy efficiency across mobile and embedded processor designs.

The authors' abstract, as published at the source. ACM Transactions on Architecture and Code Optimization, 2026 · DOI ↗