· 2013
GPUWattch
- 498citations
- 2013year
Short summary
GPUWattch, a new GPGPU power model, achieves cycle-level accuracy within 9.9% and 13.4% of real hardware measurements for GTX 480 and Quadro FX5600, respectively, by abstracting microarchitectural parameters.
AI-generated from the title and abstract; the full text is not read.
Key points
- GPUWattch is a configurable, cycle-level GPGPU power model.
- Model error is within 9.9% (GTX 480) and 13.4% (Quadro FX5600) of hardware measurements.
- Traditional DVFS reduces GPU energy consumption by 14.4% using within-kernel variations.
- Finer-grained cluster-level DVFS improves savings by 6.6% to 13.6%.
- Clock gating inactive lanes reduces dynamic power by 11.2% during divergence.
AI-generated from the title and abstract; the full text is not read.
Abstract
General-purpose GPUs (GPGPUs) are becoming prevalent in mainstream computing, and performance per watt has emerged as a more crucial evaluation metric than peak performance. As such, GPU architects require robust tools that will enable them to quickly explore new ways to optimize GPGPUs for energy efficiency. We propose a new GPGPU power model that is configurable, capable of cycle-level calculations, and carefully validated against real hardware measurements. To achieve configurability, we use a bottom-up methodology and abstract parameters from the microarchitectural components as the model's inputs. We developed a rigorous suite of 80 microbenchmarks that we use to bound any modeling uncertainties and inaccuracies. The power model is comprehensively validated against measurements of two commercially available GPUs, and the measured error is within 9.9% and 13.4% for the two target GPUs (GTX 480 and Quadro FX5600). The model also accurately tracks the power consumption trend over time. We integrated the power model with the cycle-level simulator GPGPU-Sim and demonstrate the energy savings by utilizing dynamic voltage and frequency scaling (DVFS) and clock gating. Traditional DVFS reduces GPU energy consumption by 14.4% by leveraging within-kernel runtime variations. More finer-grained SM cluster-level DVFS improves the energy savings from 6.6% to 13.6% for those benchmarks that show clustered execution behavior. We also show that clock gating inactive lanes during divergence reduces dynamic power by 11.2%.
The authors' abstract, as published at the source., 2013 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science