Sensors· 2026Q1
Runtime Firmware Update for 32-Bit Microcontrollers with Instruction Cache Under Concurrent Task Execution
- 0citations
- Q1SCImago
- 2026year
Short summary
A new runtime firmware update mechanism for 32-bit embedded systems allows dynamic reprogramming without reboot, preserving concurrent task execution for intelligent sensors and IoT devices.
AI-generated from the title and abstract; the full text is not read.
Key points
- Enables runtime firmware updates for 32-bit embedded systems without reboot.
- Preserves concurrent task execution, crucial for high-availability applications.
- Function-level updates reduced patch size to ~35% of application-level updates.
- Row-level updates reduced maximum unavailability to ~16 ms.
- Includes instruction cache invalidation, task validation, and fault recovery.
AI-generated from the title and abstract; the full text is not read.
Abstract
Smart sensor devices increasingly require remote firmware updates to deploy new functionality, security patches and algorithmic improvements without interrupting services. Runtime firmware updates remain a significant challenge in embedded sensing systems, particularly in real-time and high-availability applications where service interruption and system reboot are undesirable. This paper presents an innovative runtime firmware update mechanism for 32-bit embedded systems architecture and integrated with a custom Runtime Scheduler (RTS). The proposed approach enables dynamic Flash Program Memory (FPM) reprogramming without reboot while preserving concurrent task execution, making it suitable for intelligent sensors and edge-based IoT devices requiring continuous operation. Three update granularities, application, function and row levels, were implemented and experimentally evaluated. Reducing update granularity significantly decreased both system downtime and update data size. For the demonstration update developed to validate the concept, function-level updates reduced the transmitted patch size to approximately 35% of the data that would have been required for the equivalent application-level update, while row-level updates reduced the maximum continuous system unavailability time to approximately 16 ms by distributing FPM write operations across multiple RTS cycles. The mechanism also incorporates instruction cache invalidation, dynamic task validation and fault recovery procedures. Experiments using an intelligent power quality monitoring sensor testbed demonstrate its feasibility while improving availability, reducing update overhead and maintaining operational continuity.
The authors' abstract, as published at the source. Sensors, 2026 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science