· 2017
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?
- 457citations
- 2017year
Short summary
Future FPGAs, with thousands of hard floating-point units and high-bandwidth memory, could outperform GPUs for next-generation DNNs that exploit sparsity and compact data types.
AI-generated from the title and abstract; the full text is not read.
Key points
- Future FPGAs (e.g., Intel Stratix 10) will feature thousands of hard floating-point units and high-bandwidth memory.
- These FPGA advancements will bring their raw floating-point performance close to that of GPUs.
- Next-generation DNNs are evolving to exploit sparsity and use compact data types (1-2 bit).
- This evolution introduces irregular parallelism, which is challenging for GPUs but ideal for FPGA customizability.
AI-generated from the title and abstract; the full text is not read.
Abstract
Current-generation Deep Neural Networks (DNNs), such as AlexNet and VGG, rely heavily on dense floating-point matrix multiplication (GEMM), which maps well to GPUs (regular parallelism, high TFLOP/s). Because of this, GPUs are widely used for accelerating DNNs. Current FPGAs offer superior energy efficiency (Ops/Watt), but they do not offer the performance of today's GPUs on DNNs. In this paper, we look at upcoming FPGA technology advances, the rapid pace of innovation in DNN algorithms, and consider whether future high-performance FPGAs will outperform GPUs for next-generation DNNs. The upcoming Intel® 14-nm Stratix? 10 FPGAs will have thousands of hard floating-point units (DSPs) and on-chip RAMs (M20K memory blocks). They will also have high bandwidth memories (HBMs) and improved frequency (HyperFlex? core architecture). This combination of features brings FPGA raw floating point performance within striking distance of GPUs. Meanwhile, DNNs are quickly evolving. For example, recent innovations that exploit sparsity (e.g., pruning) and compact data types (e.g., 1-2 bit) result in major leaps in algorithmic efficiency. However, these innovations introduce irregular parallelism on custom data types, which are difficult for GPUs to handle but would be a great fit for FPGA's extreme customizability.
The authors' abstract, as published at the source., 2017 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science