ACS Nano· 2026Q1
Fingerprint-Expanding Gaussian Transistors for Compact Physical Unclonable Functions
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- 2026year
Short summary
A novel Fingerprint-Expanding Gaussian (FEG) transistor design uses IGZO/DNTT heterojunctions to generate multiple, bias-addressable entropy features within a single device, significantly increasing fingerprint capacity.
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Key points
- FEG transistors utilize IGZO/DNTT heterojunctions to create multiple entropy domains within a single device.
- These domains are electrically resolved across different branches of the Gaussian-like transfer curve, yielding bias-addressable fingerprints.
- An 8x8 FEG array achieved a candidate challenge space of approximately 1.10 × 10^12 CRPs.
- Enrollment-stage readout optimization enhances diffuseness and current margin while reducing redundant challenge mappings.
AI-generated from the title and abstract; the full text is not read.
Abstract
Abstract Physically unclonable functions (PUFs) enable hardware-rooted identities by converting fabrication randomness into challenge-response pairs (CRPs). However, conventional PUFs generally expose only one dominant entropy feature per cell, so fingerprint capacity commonly scales with array size. Here, a fingerprint-expanding Gaussian (FEG) transistor is used to provide multiple bias-addressable entropy features within a single device. Based on the IGZO/DNTT heterojunction FEG transistor, the electron and hole channels provide two entropy domains, while their heterojunction provides multiple electrically distinguishable disorder domains. These domains are electrically resolved across the rising branch, heterojunction-mediated peak, and falling branch of the Gaussian-like transfer curve, yielding multiple bias-addressable fingerprints with weak cross-branch correlation. In the FEG array, programmable word-line/bit-line biases selectively access these domains and reorder the currents of the cells, yielding an optimized candidate challenge space of approximately 1.10 × 1012 CRPs in an 8 × 8 array. Furthermore, enrollment-stage readout optimization improves diffuseness and current margin while suppressing redundant challenge mappings. By coupling heterojunction-induced entropy with a redundancy-suppressed voltage readout scheme, the FEG-based one-device-multiple-fingerprints PUF expands the accessible response space within a compact transistor array.
The authors' abstract, as published at the source. ACS Nano, 2026 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science