IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems· 2015Q1
A Survey and Evaluation of FPGA High-Level Synthesis Tools
- 525citations
- Q1SCImago
- 2015year
Short summary
A novel methodology was developed and applied to compare one commercial and three academic FPGA high-level synthesis (HLS) tools using C benchmarks, revealing significant differences in performance and resource utilization.
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Key points
- A novel methodology for evaluating FPGA HLS tools has been established.
- One commercial and three academic HLS tools were compared using C benchmarks.
- The evaluation assessed performance and resource utilization differences among the tools.
- The study provides an in-depth analysis of recent HLS tool offerings and research areas.
AI-generated from the title and abstract; the full text is not read.
Abstract
High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</monospace> benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.
The authors' abstract, as published at the source. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science