IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems· 2015Q1
A Survey and Evaluation of FPGA High-Level Synthesis Tools
- 525citations
- Q1SCImago
- 2015year
Short summary
A novel methodology was developed and applied to compare one commercial and three academic FPGA high-level synthesis (HLS) tools using C benchmarks, revealing significant differences in performance and resource utilization.
AI-generated from the title and abstract; the full text is not read.
TakeawaysIn the app
Key pointsIn the app
Ask the paperIn the app
The rest is in the Pofolia app
Takeaways, key points and questions to the paper; new summaries every day for your field. Free.
Sign in on the web to openField: Hardware and Architecture
Hardware and ArchitectureComputer Science