A robustness evaluation model for dynamic SEE testing in SRAM-based Xilinx UltraScale+ Field-Programmable Gate Arrays (FPGAs)

Abstract

SRAM-based FPGAs are widely deployed in radiation-prone environments but remain susceptible to single-event effects (SEE). This work develops and validates an analytical framework for evaluating the robustness of FPGA circuit implementations in Xilinx Virtex® UltraScale+™ FPGAs fabricated in 16 nm FinFET technology. By treating configurable logic block (CLB) and interconnect (INT) resources as independent contributors, the framework links their experimentally measured, resource-dependent SEU sensitivities to the probability of application-level functional failure. Static heavy-ion irradiation provides CLB and INT SEU parameters, which are then combined with implementation-dependent resource utilization to predict user-defined logic functional interrupt (ULFI) rates and mean time to failure (MTTF). A dynamic shift-register testbench is used as a controlled validation benchmark, demonstrating that the distribution of flip-flops (FF) across CLBs strongly influences ULFI susceptibility: higher flip-flop density per CLB, consistent with Vivado’s default placement, reduces interconnect usage and improves functional robustness. The proposed framework thus enables quantitative estimation of ULFI risk for the evaluated FPGA implementations from static single-event upset (SEU) data and supports informed choices of implementation strategy and scrubbing policy in space-grade FPGA systems.

The authors' abstract, as published at the source. Microelectronics Reliability, 2026 · DOI ↗