IEEE Transactions on Information Forensics and Security· 2013Q1
PUF Modeling Attacks on Simulated and Silicon Data
- 624citations
- Q1SCImago
- 2013year
Short summary
Machine learning attacks can successfully model strong Physical Unclonable Functions (PUFs), impersonating them with high accuracy on both simulated and silicon data.
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Key points
- Machine learning models can impersonate strong PUFs by learning their challenge-response behavior.
- Attacks were successful on standard Arbiter PUFs of arbitrary sizes and other strong PUF variants up to certain complexities.
- Proofs of concept were conducted on over four million silicon CRPs from FPGAs and ASICs, validating models trained on simulated data.
- The performance on silicon data closely matched simulated data, confirming previous conjectures.
AI-generated from the title and abstract; the full text is not read.
Abstract
We discuss numerical modeling attacks on several proposed strong physical unclonable functions (PUFs). Given a set of challenge-response pairs (CRPs) of a Strong PUF, the goal of our attacks is to construct a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs. If successful, this algorithm can subsequently impersonate the Strong PUF, and can be cloned and distributed arbitrarily. It breaks the security of any applications that rest on the Strong PUF's unpredictability and physical unclonability. Our method is less relevant for other PUF types such as Weak PUFs. The Strong PUFs that we could attack successfully include standard Arbiter PUFs of essentially arbitrary sizes, and XOR Arbiter PUFs, Lightweight Secure PUFs, and Feed-Forward Arbiter PUFs up to certain sizes and complexities. We also investigate the hardness of certain Ring Oscillator PUF architectures in typical Strong PUF applications. Our attacks are based upon various machine learning techniques, including a specially tailored variant of logistic regression and evolution strategies. Our results are mostly obtained on CRPs from numerical simulations that use established digital models of the respective PUFs. For a subset of the considered PUFs-namely standard Arbiter PUFs and XOR Arbiter PUFs-we also lead proofs of concept on silicon data from both FPGAs and ASICs. Over four million silicon CRPs are used in this process. The performance on silicon CRPs is very close to simulated CRPs, confirming a conjecture from earlier versions of this work. Our findings lead to new design requirements for secure electrical Strong PUFs, and will be useful to PUF designers and attackers alike.
The authors' abstract, as published at the source. IEEE Transactions on Information Forensics and Security, 2013 · DOI ↗
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Field: Hardware and Architecture
Hardware and ArchitectureComputer Science